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nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 1 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. 184pin one bank registered ddr sdram module based on 64mx4 ddr sdram features ? 184 - pin registered 8 - byte dual in - line memory module ? 64 mx 72 double data rate (ddr) sdram dimm ? performance : pc1600 pc2100 speed sort - 8b - 75b - 7k dimm cas latency 3 3.5 3 unit f ck clock frequency 100 133 133 mhz t ck clock cycle 10 7.5 7.5 ns f dq dq burst frequency 200 266 266 mhz ? intended for 100 mhz and 133 mhz applications ? inputs and outputs are sstl - 2 compatible ? v d d = 2.5volt 0.2, v ddq = 2.5volt 0.2 ? single pulsed ras interface ? sdrams have 4 internal banks for concurrent operation ? module has one physical bank ? differential clock inputs ? data is read or written on both clock edges ? bi - directional data strobe with one clock cycle preamble and one - half clock post - amble ? address and control signals are fully synchronous to positive clock edge ? programmable operation: - dimm cas latency: 3 , 3 .5 - burst type: sequential or interleave - burst length: 2, 4, 8 - operation: burst read and write ? auto refresh (cbr) and self refresh modes ? automatic and controlled precharge commands ? 1 3 /1 1 /2 addressing (row/column/bank) ? 7.8 s max. average periodic refresh interval ? seri al presence detect ? gold contacts ? sdrams in 66 - pin tsop type ii package description nt 512 d 72 s 4p a0g r is a regist ered 184 - pin double data rate (ddr) synchronous dram dual in - line memory module (dimm), organized as a one - bank high - speed memory array. the 64 mx 72 module is a single - bank dimm that uses eight een 64 mx 4 ddr sdrams in 400 mil tsop packages. the dimm achieves high - speed data transfer rates of up to 266mhz. the dimm is intended for use in applications operating from 100 mhz to 133 mhz clock spe eds with data rates of 200 to 266 mhz. clock enable cke0 controls all devices on the dimm. prior to any access operation, the device cas latency and burst type/ length/operation type must be programmed into the dimm by address inputs a0 - a1 2 and i/o inputs ba0 and ba1 using the mode register set cycle. these dimms are manufactured using raw cards developed for broad industry use as reference designs. the use of these common design files minimizes electrical variation between suppliers. the dimm uses serial presence detects implemented via a serial eeprom using the two - pin iic protocol. the first 128 bytes of serial pd data are programmed and locked during module assembly. the last 128 bytes are available to the customer. all nanya 184 ddr s dram dimms provide a high - performance, flexible 8 - byte interface in a 5.25? long space - saving footprint. ordering information part number speed organization leads power component module 143mhz (7ns @ cl = 2.5 ) nt 512 d 72 s 4p a0g r - 7k 133mhz (7.5ns @ cl= 2 ) ddr266a pc2100 133mhz (7.5ns @ cl= 2.5 ) nt 512 d 72 s 4p a0g r - 75b 100mhz (10ns @ cl = 2 ) ddr266b pc2100 125mhz (8ns @ cl = 2.5 ) nt 512 d 72 s 4p a0g r - 8b 100mhz (10ns @ cl = 2 ) ddr200 pc1600 64 mx72 gold 2.5v
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 2 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. pin descripti on ck0, ck0 differential clock inputs dq0 - dq63 data input/output cke0 clock enable cb0 - cb7 check bit data input/output ras row address strobe dqs0 - dqs17 bidirectional data strobes cas column address strobe v dd power ( 2.5 v) we write enable v ddq supply voltage for dqs(2.5v) s0 chip selects v ss ground a0 - a9, a11 ,a12 address inputs nc no connect a10/ap address input/autoprecharge scl serial presence d etect clock input ba0, ba1 sdram bank address inputs sda serial presence detect data input/output reset reset pin sa0 - 2 serial presence detect address inputs v ref ref. voltage for sstl_2 inputs v ddid v dd identification flag. v ddspd serial eeprom positive power suppl y(2.5v) pinout pin front pin front pin front pin back pin back pin back 1 v ref 32 a5 62 v ddq 93 v ss 124 v ss 154 ras 2 dq0 33 dq24 63 we 94 dq4 125 a6 155 dq45 3 v ss 34 v ss 64 dq41 95 dq5 126 dq28 156 v ddq 4 dq1 35 dq25 65 cas 96 v ddq 127 dq29 157 s0 5 dq s0 36 dq s3 66 v ss 97 dq s9 128 v ddq 158 nc 6 dq2 37 a 4 67 dqs5 98 dq6 129 dqs12 159 dqs14 7 v dd 38 v dd 68 dq42 99 dq7 130 a 3 160 v ss 8 dq 3 39 dq2 6 69 dq43 100 v ss 131 dq30 161 dq46 9 nc 40 dq27 70 v dd 101 nc 132 v ss 162 dq47 10 reset 41 a 2 71 nc 102 nc 133 dq31 163 nc 11 v ss 42 v ss 72 dq 48 103 nc 134 cb4 164 v ddq 12 dq8 43 a1 73 dq49 104 v ddq 135 cb5 165 dq52 13 dq9 44 cb0 74 v ss 105 dq1 2 136 v ddq 166 dq53 14 dq s1 45 cb1 75 nc 106 dq1 3 137 ck0 167 nc 15 v ddq 46 v dd 76 nc 107 dqs10 138 ck0 168 v dd 16 nc 47 dq s8 77 v ddq 108 v dd 139 v ss 169 dqs15 17 nc 48 a0 78 dqs6 109 dq1 4 140 dqs17 170 dq54 18 v ss 49 cb2 79 dq 50 110 dq1 5 141 a10 171 dq55 19 dq1 0 50 v ss 80 dq 51 111 nc 142 cb6 172 v ddq 20 dq1 1 51 cb3 81 v ss 112 v ddq 143 v ddq 173 nc 21 c ke0 52 ba1 82 v ddid 113 nc 144 cb7 174 dq60 22 v ddq key 83 dq56 114 dq20 key 175 dq61 23 dq1 6 53 dq 32 84 dq57 115 a12 145 v ss 176 v ss 24 dq1 7 54 v ddq 85 v dd 116 v ss 146 dq36 177 dqs16 25 dq s2 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 v ss 56 dqs4 87 dq58 118 a11 148 v dd 179 dq63 27 a9 57 dq34 88 dq59 119 dqs11 149 dqs13 180 v ddq 28 dq 18 58 v ss 8 9 v ss 120 v dd 150 dq38 181 sa0 29 a7 59 ba0 90 nc 121 dq22 151 dq39 182 sa1 30 v ddq 60 dq35 91 sda 122 a8 152 v ss 183 sa2 31 dq 19 61 dq40 92 scl 123 dq23 153 dq44 184 v ddspd
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 3 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. input/output functional description symbol type polarity function c k0 (sstl) positive edge the positive line of the differential pair of system clock inputs which drives the input to the on - dimm pll. all the ddr sdram address and control inputs are sampled on the rising edge of their associated clocks. ck0 (sstl) negative edge the negative line of the differential pair of system clock inputs which drives the input to the on - dimm pll. cke0 (sstl) active high activates the sdram ck signal when high and deactivates the ck signal when low. by deactivatin g the clocks, cke low initiates the power down mode, or the self refresh mode. s0 (sstl) active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled , new commands are ignored but previous operations continue. ras , cas , we (sstl) active low when sampled at the positive rising edge of the clock, ras , cas , we define the operation to be executed by the sdram. v ref supply reference voltage for sstl - 2 inputs v ddq supply isolated power supply for the ddr sdram output buffers to provide improved noise immunity ba0, ba1 (sstl) - selects wh ich sdram bank is to be active. a0 - a9 a10/ap a11 , a12 (sstl) - during a bank activate command cycle, a0 - a1 2 defines the row address (ra0 - ra1 2 ) when sampled at the rising clock edge. during a read or write command cycle, a0 - a 9, a11 defines the column add ress (ca0 - ca 10 ) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0/ba1 define the bank to be p recharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) to precharge. if ap is high all 4 banks will be precharged regardless of the state of ba0/ba1. if ap is lo w, then ba0/ba1 are used to define which bank to pre - charge. dq0 - dq63 , (sstl) - data and check bit input/output pins operate in the same manner as on conventional drams. dq0 ? dq 63 cb0 ? cb7 (sstl) active high data and check bit input/output pins. chec k bits are only applicable on the x72 dimm configurations. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic dq s 0 ? dq s17 (sstl) negative and positive edge data strobe for input and output data reset (l vc - mos) active low sa0 ? sa2 - address inputs. connected to either v dd or v ss on the system board to configure the serial presence detect eeprom address. sda - this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor m ust be connected from the sda bus line to v dd to act as a pullup. scl - this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v dd to act as a pullup. v ddspd supply serial eeprom positi ve power supply.
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 4 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. functional block diagram ( 1 bank, 64 mx 4 ddr sdrams ) a0 - a12 : sdrams d0 - d17 ba0-ba1 : sdrams d0 - d17 v ss ras : sdrams d0- d17 cke : sdrams d0- d17 cas : sdrams d0- d17 we : sdrams d0- d17 dqs0 dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 serial pd dm rs0 i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm r e g i s t e r ba0-ba1 a0 - a12 ras cas cke0 we cs0 pck pck ra0-ra12 rba0-rba1 rras rcas rcke0a rwe rs0 s0 : sdrams d0 - d17 reset i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm i/o 0 i/o 1 i/o 3 i/o 2 dqs cs d0 dm notes : 1. dq-to-i/o wiring may be changed within a byte 2. dq/dqs/dm/cke/cs relationships are maintained as shown. 3. dq/dqs resistors are 22 ohms. 4. vddid strap connections (for memory device vdd,vddq): strap out (open): vdd = vddq strap in (vss): vdd 1 vddq. 5. address and control resistors are 22ohms. v ddspd v ddq v dd v ref v ss v ddid d0 - d17 d0 - d17 d0 - d17 d0 - d17 strap : see note4 serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 * wire per clock loading table/wiring diagrams * ck0, ck0 --------- pll* dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq48 dq49 dq50 dq51 dq56 dq57 dq58 dq59 cb0 cb1 cb2 cb3 dqs1 dqs2 dqs3 dqs4 dqs5 dqs6 dqs7 dqs8 dm0/dqs9 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq52 dq53 dq54 dq55 dq60 dq61 dq62 dq63 cb4 cb5 cb6 cb7 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm4/dqs13 dm5/dqs14 dm6/dqs15 dm7/dqs16 dm8/dqs17
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 5 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. serial presence detect -- part 1 of 2 64 mx 72 1 bank registered ddr sdram dimm based on 64 mx 4 , 4banks, 8k refresh, 2.5 v ddr sdrams with sp d spd entry value serial pd data entry (hexadecimal) note byt e description ddr266a - 7k ddr266b - 75b ddr200 - 8b ddr266a - 7k ddr266b - 75 ddr200 - 8b 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 25 6 08 2 fundamental memory type sdram ddr 07 3 number of row addresses on assembly 13 0d 4 number of column addresses on assembly 11 0b 5 number of dimm bank 1 01 6. data width of assembly x72 4 8 7 data width of assembly (cont?) x72 00 8 volta ge interface level of this assembly sstl 2.5v 04 9 ddr sdram device cycle time at cl=2.5 7ns 7.5ns 8ns 70 75 80 10 ddr sdram device access time from clock at cl=2.5 0.75ns 0.75ns 0.8ns 75 75 80 11 dimm configuration type ecc 0 2 12 refresh rate/type 7.8 us / sr 8 2 13 primary ddr sdram width x 4 0 4 14 error checking ddr sdram device width x4 0 4 15 ddr sdram device attr: min c l k delay, random col access 1 clock 01 16 ddr sdram device attributes: burst length supported 2,4,8 0e 17 ddr sdram dev ice attributes: number of device banks 4 04 18 ddr sdram device attributes: cas latencies supported 2/2.5 2/2.5 2/2.5 0c 0c 0c 19 ddr sdram device attributes: cs latency 0 01 20 ddr sdram device attributes: we latency 1 02 21 ddr sdram device attri butes: differential clock, pll, register 26 22 ddr sdram device attributes: general +/ - 0.2v voltage tolerance 00 23 minimum clock cycle at cl=2 7.5ns 10ns 10ns 75 a0 a0 24 maximum data access time from clock at cl=2 0.75ns 0.75ns 0.8ns 75 75 80 25 minimum clock cycle time at cl=1 n/a 00 26 maximum data access time from clock at cl=1 n/a 00 27 minimum row precharge time( t r p ) 20ns 20ns 20ns 50 50 50 28 minimum row active to row active delay ( t r rd ) 15ns 15ns 15ns 3c 3c 3c 29 minimum ras to cas delay ( t r cd ) 20ns 20ns 20ns 50 50 50 30 minimum ras pulse width ( t ras ) 45ns 45ns 50ns 2d 2d 32 31 module bank density 512 mb 8 0 32 address and command setup time before clock 0.9ns 0.9ns 1.1ns 90 90 b0 33 address and command hold time after clock 0. 9ns 0.9ns 1 .1 ns 90 90 b0 34 data input setup time before clock 0.5ns 0.5ns 0.6ns 50 50 60 35 data input hold time after clock 0.5ns 0.5ns 0.6ns 50 50 60 36 - 61 reserved undefined 00 62 spd revision initial initial initial 00 00 00 63 checksum data df 0f 95
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 6 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. serial presence detect -- part 2 of 2 64 mx 72 1 bank registered ddr sdram dimm based on 64 mx 4 , 4banks, 8k refresh, 2.5 v ddr sdrams with sp d spd entry value serial pd data entry (hexadecimal) byte description ddr266a - 7k ddr266b - 75b ddr200 - 8b ddr266a - 7k ddr266b - 75 ddr200 - 8b note 64 - 71 manufacturer?s jeded id code nanya 7f7f7f0b 00000000 72 module manufacturing location n/a 00 73 - 90 module part number n/a n/a n/a 00 00 00 91 - 92 module revision code n/a 00 93 - 94 module manufac turing data year/week code yy/ww 1,2 95 - 98 module serial number serial number 00 99 - 255 reserved undefined 00 1. yy= binary coded decimal year code, 0 - 99(decimal) , 00 - 63(hex) 2. ww= binary coded decimal year code, 01 - 52(decimal) , 01 - 34(hex)
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 7 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to vss - 0.5 to v ddq +0.5 v v in voltage on input relative to vss - 0.5 to +2.7 v v dd voltage on vdd supply relative to vss - 0.5 to + 2.7 v v dd q voltage on vddq supply relative to vss - 0.5 to +2.7 v t a operating temperature (ambient) 0 to +70 c t stg storage temperature (plastic) - 55 to +150 c p d power dissipation 18 w i out short circuit output current 50 ma note : stresses greate r than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sec ti ons of this spe cification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance parameter symbol max. units notes input capacitance: ck0, ck0 c i1 7 pf 1 input capacitance: a0 - a1 2 , b a0, ba1, we , ras , cas , cke0, s0 c i2 7 pf 1 input capacitance: reset c i3 7 pf 1 input capacitance: sa0 - sa2, scl c i4 9 pf 1 input/output capacitance dq0 - 63; dq s0 - 1 7, cb0 - 7 c io1 10 pf 1,2 input/output capacitance: sda c io3 11 pf 1. v ddq = v dd = 2.5v 0.2v, f = 100 mhz, t a = 2 5 c , v out (dc) = v ddq /2, v out (peak to peak) = 0.2v. 2. d m inputs are grouped with i/o pins reflecting the fact that they are matched i n loading to dq and dqs to facilitate trace matching at the board level.
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 8 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. dc electrical characteristics and operating conditions ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) symbol p arameter min max units notes v dd supply voltage 2.3 2.7 v 1 v dd q i/o supply voltage 2.3 2.7 v 1 v ss , v ssq supply voltage , i/o supply voltage 0 0 v v ref /o reference voltage 0.49 x v dd q 0.51 x v dd q v 1,2 v tt i/o termination voltage (system) v ref ? 0 .04 v ref + 0.04 v 1,3 v ih(dc) input high (logic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il(dc) input low (logic0) voltage - 0.3 v ref - 0. 15 v 1 v in(dc) input voltage level, ck and ck inputs - 0.3 v ddq + 0.3 v 1 v id(dc) input differential voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1,4 i i input leakage current any input 0v v in v dd ; (all other pins not under test = 0v) - 5 5 ua 1 i oz output leakage current (dqs are disabled; 0v v out v ddq - 5 5 ua 1 i oh output high current (v out = v ddq - 0.373v, min v ref , min v tt ) - 16.8 - ma 1 i ol output low current (v out = 0 .373, max v ref , max v tt ) 16.8 - ma 1 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the t ransmitting device, and to track variations in the dc level of the same. peak - to - peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the dimm. v tt is a system supply for signal termination resistors, is expected to be se t equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck .
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 9 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. ac characteristics (notes 1 - 5 apply to the following tables; electrical characteristics and dc operating conditions, ac operating conditions, operating, standby, and refresh currents, and electrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. ref er to the ac output load circuit below. 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck, ck), and parameter specifications are guara nteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il(ac) and v ih(ac) unless otherwise specified. 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level. ac output load circuits timing reference point v tt 50 ohms 30 pf output v out ac operating conditions ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) symbol parameter/condition min max unit notes v ih(ac) input high (logic 1) voltage. v ref + 0.31 - v 1, 2 v il(ac) input low (logic 0) voltage. - v ref ? - 0.31 v 1, 2 v id(ac) input differential voltage, ck and ck inputs 0. 7 v ddq + 0.6 v 1, 2, 3 v ix(ac) input differential pair cross point voltage, ck and ck inputs (0.5*v ddq ) - 0 .2 (0.5*v ddq ) + ? 0.2 v 1, 2, 4 1. input slew rate = 1v/ n s . 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck. 4. the value of v ix is expected to equal 0.5*v ddq of the transmitt ing device and must track variations in the dc level of the same.
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 10 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. operating, standby, and refresh currents ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) symbol parameter/condition pc1600 pc2100 uni t notes i dd0 operating current : one bank; active / precharge; t rc = t rc ( min ) ; t ck = t ck ( min ) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 2190 2480 ma 1 i dd1 operating current : one bank; active / read / precharge; burst = 2; t rc = t rc ( min ) ; cl=2.5; t ck = t ck ( min ) ; i out = 0ma; address and control inputs changing once per clock cycle 2460 3000 ma 1 i dd 2p precharge power - down standby current : all banks idle; power - down m ode; cke v il ( max ) ; t ck = t ck ( min ) 1100 1100 ma 1 i dd2n idle standby current : cs 3 v ih ( min ) ; all banks idle; cke 3 v ih ( min ) ; t ck = t ck ( min ) ; address and control inputs changing once per clock cycle 1380 1610 ma 1 i dd3p active power - down sta ndby current : one bank active; power - down mode; cke v il ( max ) ; t ck = t ck ( min ) 1110 1100 ma 1 i dd3n active standby current : one bank; active / precharge; cs 3 v ih ( min ) ; cke 3 v ih ( min ) ; t rc = t ras ( max ) ; t ck = t ck ( min ) ; dq, dm, and dqs input s changing twice per clock cycle; address and control inputs changing once per clock cycle 1740 2088 ma 1 i dd4r operating current : one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs out puts changing twice per clock cycle; cl = 2.5; t ck = t ck ( min ) ; i out = 0ma 3180 4036 ma 1 i dd4w operating current : one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing t wice per clock cycle; cl=2.5; t ck = t ck ( min ) 2910 2850 ma 1 t rc = t rfc ( min ) 3720 3950 ma i dd 5 auto - refresh current : t rc = 7.8 s 1144 1144 ma 1,3 i dd6 self - refresh current : cke ?0.2v 61 61 ma 1 1. i dd specifications are tested after the device is properly initialized. 2. enables on - chip refresh and address counters. 3 . current at 7.8 s is time averaged value of i dd5 at t rfc ( min ) and i dd2p over 7.8 s.
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 11 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. ac timing speci fi cations for ddr sdram devices used on module ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) (part 1 of 2) - 7k - 75b - 8b symbol parameter min. max. min. max. min. max. unit note s t ac dq output access time from ck/ ck - 0.75 +0.75 - 0.75 +0.75 - 0.8 +0 .8 ns 1,2,3,4 t dqsck dqs output access time from ck/ ck - 0.75 +0.75 - 0.75 +0.75 - 0.8 +0.8 ns 1,2,3,4 t ch ck high - level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1,2,3,4 t cl ck low - level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1,2,3,4 t ck cl=2.5 7 12 7.5 12 8 12 ns 1,2,3,4 t ck clock cycle time cl=2 7.5 12 10 12 10 12 ns 1,2,3,4 t dh dq and dm input hold time 0.5 0.5 0.6 ns 1,2,3,4 ,1 5 , 16 t ds dq and dm input setup time 0.5 0.5 0.6 ns 1,2,3,4 ,1 5 , 16 t dipw dq and dm input pulse wid th (each input) 1.75 1.75 2 ns 1,2,3,4 t hz data - out high - impedance time from ck/ ck - 0.75 +0.75 - 0.75 +0.75 - 0.8 +0.8 ns 1, 2, 3, 4, 5 t lz data - out low - impedance time from ck / ck - 0.75 +0.75 - 0.75 +0.75 - 0.8 +0. 8 ns 1, 2, 3, 4, 5 t dqsq dqs - dq skew (dqs & associated dq signals) 0.5 0.5 0.6 ns 1,2,3,4 t dqsqa dqs - dq skew (dqs & all dq signals) 0.5 0.5 0.6 ns 1,2,3,4 t hp minimum half clk period for any given cycle; defined by clk high (t ch ) or clk low (t cl ) time t ch or t cl t ch or t cl t ch or t cl t ck 1,2,3,4 t qh data output hold time from dqs t hp - 0.75ns t hp - 0.75ns t hp - 1.0ns t ck 1,2,3,4 t dqss write command to 1st dqs latching transition 0.75 1.25 0.75 1.25 0.75 1.25 t ck 1,2,3,4 t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 0.35 0.35 t ck 1,2,3,4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 0.2 t ck 1,2,3,4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 0.2 t ck 1,2,3,4 t mrd mode register set command cycle time 14 15 16 ns 1,2,3,4 t wpres write preamble setup time 0 0 0 ns 1, 2, 3, 4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1, 2, 3, 4, 6 t wpre write preamble 0.25 0.25 0.25 t ck 1,2,3,4 t ih address and control input hold time (fast slew rate) 0.9 1.1 1.1 ns 2, 3, 4, 9 , 1 1 , 1 2 t is address and control input setup time (fast slew rate) 0.9 1.1 1.1 ns 2, 3, 4, 9 , 11 , 1 2 t ih address and control input hold time (slow slew rate) 1.0 1.1 1.1 ns 2, 3, 4, 1 0 , 1 1 , 1 2 , 14
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 12 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. ac timing specifications for ddr sdram devices used on module ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) (part 2 of 2) - 7k - 75b - 8b symbol parameter min. max. min. max. min. max. unit note s t is a ddress and control input setup time (slow slewrate) 1.0 1.0 1.1 ns 2, 3, 4, 1 0 , 1 1 , 12 , 14 t ipw input pulse width 2.2 2.2 - ns 2, 3, 4, 12 t rpre read preamble 0.9 1.1 0.9 1.1 0.9 1.1 t ck 1,2,3,4 t rpst read postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1,2,3,4 t ras active to precharge command 45 120,000 45 120,000 50 120,000 ns 1,2,3,4 t rc active to active/auto - refresh command period 65 65 70 ns 1,2,3,4 t rfc auto - refresh to active/auto - refresh command period 75 75 80 ns 1,2,3,4 t rcd active to read or write delay 20 20 20 ns 1,2,3,4 t rap active to read command with autoprecharge 20 20 20 ns 1,2,3,4 t rp precharge command period 20 20 20 ns 1,2,3,4 t rrd active bank a to active bank b command 15 15 15 ns 1,2,3,4 t wr write recover y time 15 15 15 ns 1,2,3,4 t dal auto precharge write recovery + precharge time (t wr / t ck ) + (t rp / t ck ) (t wr / t ck ) + (t rp / t ck ) (t wr / t ck ) + (t rp / t ck ) t ck 1, 2, 3, 4, 1 3 t wtr internal write to read command delay 1 1 1 t ck 1,2 , 3,4 t xsnr exit self - refresh to non - read command 75 75 80 ns 1,2 , 3,4 t xsrd exit self - refresh to read command 200 200 200 t ck 1,2 , 3,4 t refi average periodic refresh interval 7.8 7.8 7.8 s 1, 2, 3, 4, 8
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 13 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. ac timing specification notes 1. input sl ew rate = 1v/ns. 2. the ck/ ck input reference level (for timing reference to ck/ ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ ck , is v ref . 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same acces s time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the devic e operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transitio n is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi - z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 9 . for command/address input slew rate >= 1.0 v/ns. slew rate is measured between v oh (ac) and v ol ( ac). 10 . for command/address input slew rate >= 0.5 v/ns and < 1.0 v/ns. slew rate is measured between v oh (ac) and v ol (ac). 1 1 . ck/ ck slew rates are >= 1.0 v/ns. 1 2 . these parameters guarantee device timing, but they are not necessari ly tested on each device, and they may be guaranteed by design or tester characterization. 1 3 . for each of the terms in parentheses, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. for exam ple, for pc2100 at cl= 2.5, t dal = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 1 4 . an input setup and hold time derating table is used to increase t is and t ih in the case where the input slew rate is below 0.5 v/ns. input slew rate ? delta ( t i s ) delta ( t i h ) unit note 0.5 v/ns 0 0 ps 1,2 0. 4 v/ns +50 0 ps 1,2 0. 3 v/ns +100 0 ps 1,2 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. thes e derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 1 5 . an input setup and hold time derating table is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/ns. input slew rate delta ( t d s ) delta ( t dh ) unit note 0.5 v/ns 0 0 ps 1,2 0. 4 v/ns +75 +75 ps 1,2 0. 3 v/ns +150 +150 ps 1,2 1. i/o slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 1 6 . an i/o delta rise, fall derating table is used to increase t ds and t dh in th e case where dq, dm, and dqs slew rates differ. delta rise and fall rate delta ( t d s ) delta ( t dh ) unit note 0.0 ns/v 0 0 ps 1,2,3,4 0.25 ns/v +50 +50 ps 1,2,3,4 0.5 ns/v +100 +100 ps 1,2,3,4 1. input slew rate is based on the lesser of the slew rate s determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. input slew rate is based on the larger of ac to ac delta rise, fall rate and dc to dc delta rise, fall rate. 3. the delta rise, fall rate is calc ulated as: [1/(slew rate 1)] - [1/(slew rate 2)] for example: slew rate 1 = 0.5 v/ns; slew rate 2 = 0.4 v/ns . delta rise, fall = (1/0.5) - (1/0.4) [ns/v] = - 0.5 ns/v using the table above, this would result in an increase in t ds and t dh of 100 ps. 4. the se derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
nt 512d72s4pa0gr 512mb : 64 m x 72 register ed ddr sdram dimm prelimin ary 0 8/0 1 14 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without no tice. package dimensions note : all dimensions are typical unless otherwise stated. 133.35 131.35 128.95 (2x) 4.00 front side 1.80 detail a 0.050 detail b 1.00 width 3.99 back 43.33 17.80 10.0 register register pll 2.3 (front) 4.24 1.27 unit : millimeters(inches) 5.250 5.171 5.077 0.157 0.091 0.700 1.700 0.157 max. 0.167 0.050 0.098 q 2.5 0.394 0.071 detail a detail b 3.80 0.15 0.157 4.00 0.039 1.27 pitch

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